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| STK14EC16 Preliminary FEATURES * 15, 25, 45 ns Read Access and R/W Cycle Time * Unlimited Read/Write Endurance * Automatic Non-volatile STORE on Power Loss * Non-Volatile STORE Under Hardware or Software Control * Automatic RECALL to SRAM on Power Up * Unlimited RECALL Cycles * 200K STORE Endurance * 20-Year Non-volatile Data Retention * Single 3.0V +20%, -10% Operation * Commercial, Industrial Temperatures * 44-pin or 54-pin 400-mil TSOPII Packages (RoHSCompliant) * 48-ball Fine Pitch Ball Grid Array (FBGA) 256Kx16 AutoStore nvSRAM DESCRIPTION The Simtek STK14EC16 is a 4MB fast static RAM with a non-volatile Quantum Trap storage element included with each memory cell. The SRAM provides the fast access & cycle times, ease of use and unlimited read & write endurance of a normal SRAM. Data transfers automatically to the non-volatile storage cells when power loss is detected (the STORE operation). On power up, data is automatically restored to the SRAM (the RECALL operation). Both STORE and RECALL operations are also available under software control. The Simtek nvSRAM is the highest performance, most reliable non-volatile memory available. BLOCK DIAGRAM A0 A1 A2 A3 A4 A5 A6 A7 A8 A17 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 Row Decoder EEPROM Array 2048 x 2048 STORE SRAM Array 2048 x 2048 Store/ Recall Control RECALL Power Control VCC VCAP HSB Input Buffers Software Detect A0 - A17 Column I/O Column Decoder G W A9 A10 A11 A12 A13 A14 A15 A16 E UB Pachuco Boys LB This is a product in development that has fixed target specifications that are subject to change pending characterization results. SIMTEK Confidential & Proprietary 1 Document Control #ML0061 Rev 1.1 Jan, 2008 STK14EC16 Truth Table for SRAM Operations Operating Mode Standby/not selected E H L Internal Read L Lower Byte Read Upper Byte Read Word Read Lower Byte Write Upper Byte Write Word Write L L L L L L H H H H H H H X H H H L L L X L L L X X X H L H L L H L H H L L H L L High-Z Data Outputs Low-Z High-Z Data Outputs Low-Z Data Inputs High-Z High-Z Data Inputs High-Z HSB H H W X H G X H LB X X UB X X DQ0-DQ7 High-Z High-Z Preliminary DQ8-DQ15 High-Z High-Z High-Z High-Z Data Outputs Low-Z Data Outputs Low-Z High-Z Data Inputs High-Z Data Inputs High-Z Document Control #ML0061 Rev 1.1 Jan, 2008 2 Simtek Confidential Preliminary STK14EC16 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A17 A16 A15 G UB LB DQ15 DQ14 DQ13 DQ12 VSS VCC DQ11 DQ10 DQ9 DQ8 VCAP A14 A13 A12 A11 A10 NC NC A0 A1 A2 A3 A4 E DQ0 DQ1 DQ2 DQ3 VCC VSS DQ4 DQ5 DQ6 DQ7 W A5 A6 A7 A8 A9 NC NC NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 54 53 52 51 50 49 48 47 46 45 44 1 HSB NC A17 A16 A15 G UB LB DQ15 DQ14 DQ13 DQ12 VSS VCC DQ11 DQ10 DQ9 DQ8 VCAP A14 A13 A12 A11 A10 NC NC NC 2 3 4 5 6 A0 A1 A2 A3 A4 E DQ0 DQ1 DQ2 DQ3 VCC VSS DQ4 DQ5 DQ6 DQ7 W A5 A6 A7 A8 A9 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 LB DQ 8 G UB A0 A3 A5 A17 A1 A4 A6 A7 A16 A15 A13 A10 A2 E NC DQ 0 A B C D E F G H DQ 9 DQ10 VSS DQ11 DQ1 DQ 2 DQ3 DQ4 VCC VSS (TOP) (TOP) 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 VCC DQ12 VCAP DQ14 DQ13 DQ15 HSB NC A8 A14 A12 A9 DQ5 DQ 6 W A11 DQ7 NC (TOP) 48-Ball FBGA 44-Pin TSOP-II (See full mechanical drawings on pages 18 - 20) 54-Pin TSOP-II PIN DESCRIPTIONS Pin Name A17-A0 DQ15-DQ0 E LB UB W G VCC HSB Input I/O Input Input Input Input Input Power Supply I/O I/O Description Address: The 18 address inputs select one of 262,144 words in the nvSRAM array Data: Bi-directional 16-bit data bus for accessing the nvSRAM Chip Enable: The active low E input selects the device Byte Write Select Input: Controls DQ7-DQ0 (unselected byte will not write or read). Byte Write Select Input: Controls DQ15-DQ8 (unselected byte will not write or read). Write Enable: The active low W enables data on the DQ pins to be written to the address location latched by the falling edge of E Output Enable: The active low G input enables the data output buffers during read cycles. De-asserting G high causes the DQ pins to tri-state. Power: 3.0V +20%, -10% Hardware Store Busy: When low this output indicates a Store is in progress (also low during power up while busy). When pulled low external to the chip, it will initiate a nonvolatile STORE operation. A weak pull up resistor keeps this pin high if not connected. (Connection Optional). Autostore Capacitor: Supplies power to the nvSRAM during a power loss to store data from SRAM to nonvolatile storage elements. Ground This pin is not connected to the die. (Do not connect in design; reserved for future use) VCAP VSS NC Power Supply Power Supply No Connect Document Control #ML0061 Rev 1.1 Jan, 2008 3 Simtek Confidential STK14EC16 ABSOLUTE MAXIMUM RATINGSa Voltage on Input Relative to Ground . . . . . . . . . . . . . -0.5V to 4.1V Voltage on Input Relative to VSS . . . . . . . . . .-0.5V to (VCC + 0.5V) Voltage on DQ0-7 or HSB . . . . . . . . . . . . . . . .-0.5V to (VCC + 0.5V) Temperature under Bias. . . . . . . . . . . . . . . . . . . . . .-55C to 125C Junction Temperature . . . . . . . . . . . . . . . . . . . . . . .-55C to 140C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65C to 150C Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1W DC Output Current (1 output at a time, 1s duration) . . . . . . . 15mA Preliminary Note a: Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. TF (TSOP-II 44) PACKAGE THERMAL CHARACTERISTICS jc tbd; ja tbd [0fpm], tbd [200fpm], tbd C/W [500fpm]. UF (TSOP-II 54) PACKAGE THERMAL CHARACTERISTICS jc tbd; ja tbd [0fpm], tbd [200fpm], tbd C/W [500fpm]. BF (FBGA48) PACKAGE THERMAL CHARACTERISTICS jc tbd C/W; ja tbd [0fpm], tbd [200fpm], tbd C/W [500fpm]. DC CHARACTERISTICS COMMERCIAL SYMBOL ICC1 PARAMETER MIN Average VCC Current 70 65 50 75 70 52 mA mA mA MAX MIN MAX INDUSTRIAL UNITS (VCC = 2.7V-3.6V) NOTES tAVAV = 15ns tAVAV = 25ns tAVAV = 45ns Dependent on output loading and cycle rate. Values obtained without output loads. All Inputs Don't Care, VCC = max Average current for duration of STORE cycle (tSTORE) W (V CC - 0.2V) All Other Inputs Cycling at CMOS Levels Dependent on output loading and cycle rate. Values obtained without output loads. All Inputs Don't Care Average current for duration of STORE cycle (tSTORE) E (VCC -0.2V) All Others VIN 0.2V or (VCC-0.2V) Standby current level after nonvolatile cycle complete VCC = max VIN = VSS to VCC VCC = max VIN = VSS to VCC, E or G VIH All Inputs All Inputs IOUT = - 2mA (except HSB) IOUT = 4mA ICC2 Average VCC Current during STORE 6 6 mA ICC3 Average VCC Current at tAVAV = 200ns 3V, 25C, Typical 26 26 mA ICC4 Average VCAP Current during Auto Store Cycle VCC Standby Current (Standby, Stable CMOS Levels) 6 6 mA ISB 3 3 mA IILK IOLK VIH VIL VOH VOL TA VCC VCAP NVC DATAR Input Leakage Current Off-State Output Leakage Current Input Logic "1" Voltage Input Logic "0" Voltage Output Logic "1" Voltage Output Logic "0" Voltage Operating Temperature Operating Voltage Storage Capacitance Nonvolatile STORE operations Data Retention 0 2.7 61 200 20 2.0 VSS -0.5 2.4 1 1 VCC + 0.5 0.8 2.0 VSS -0.5 2.4 0.4 70 3.6 134 - 40 2.7 61 200 20 1 1 VCC + 0.5 0.8 A A V V V 0.4 85 3.6 180 V C V F K Years 3.3V nominal Between VCAP pin and VSS, 5V rated (Nom. 68 F to 150 F +20%, - 10%) @ 55 deg C Note: The HSB pin has IOUT=-10 uA for VOH of 2.4 V. This parameter is characterized but not tested. Document Control #ML0061 Rev 1.1 Jan, 2008 4 Simtek Confidential Preliminary AC TEST CONDITIONS Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to 3V Input Rise and Fall Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5ns Input and Output Timing Reference Levels . . . . . . . . . . . . . . . 1.5V Output Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Figure 1 and 2 STK14EC16 CAPACITANCEb SYMBOL CIN COUT PARAMETER Input Capacitance Output Capacitance (TA = 25C, f = 1.0MHz) MAX 7 7 UNITS pF pF CONDITIONS V = 0 to 3V V = 0 to 3V Note b: These parameters are guaranteed but not tested. 3.0V 577 Ohms OUTPUT 789 Ohms 30 pF INCLUDING SCOPE AND FIXTURE Figure 1: AC Output Loading 3.0V 577 Ohms OUTPUT 789 Ohms 5 pF INCLUDING SCOPE AND FIXTURE Figure 2: AC Output Loading for Tristate Specs (tHZ, tLZ, tWLQZ, tWHQZ, tGLQX, tGHQZ) Document Control #ML0061 Rev 1.1 Jan, 2008 5 Simtek Confidential STK14EC16 SRAM READ CYCLES #1 & #2 NO. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 tAXQXd tAVAVc tAVQVd SYMBOLS #1 #2 tELQV tELEHc tAVQVd tGLQV tBLQV tAXQXd tELQX tEHQZe tBLQX tGLQX tGHQZe tBHQZe tELICCHb tEHICCLb tPA tPS tOLZ tOHZ tOH tLZ tHZ Alt. tACS tRC tAA tOE PARAMETER Chip Enable Access Time Read Cycle Time Address Access Time Output Enable to Data Valid Byte Enable to Data Valid Output Hold after Address Change Address Change or Chip Enable to Output Active Address Change or Chip Disable to Output Inactive Byte Enable to Output Active Output Enable to Output Active Output Disable to Output Inactive Byte Enable to Output Inactive Chip Enable to Power Active Chip Disable to Power Standby 0 15 0 7 7 0 3 3 7 7 0 15 15 10 10 3 3 STK14EC16-15 MIN MAX 15 25 MIN Preliminary STK14EC16-25 MAX 25 STK14EC16-45 MIN MAX 45 45 UNITS ns ns 25 12 12 3 3 10 10 0 10 10 0 25 45 20 20 ns ns ns ns ns 15 15 ns ns ns 15 15 ns ns ns 45 ns Note c: Note d: Note e: Note f: W must be high during SRAM READ cycles. Device is continuously selected with E and G both low, LB and UB select bytes read. Measured 200mV from steady state output voltage. HSB must remain high during READ and WRITE cycles. SRAM READ CYCLE #1: Address Controlledc,d,f tAVAV (2) Address tAVQV Data Output Previous Data Valid tAXQX (6) Address Valid (3) Output Data Valid SRAM READ CYCLE #2: E and G Controlledc,f ADDR ESS t E LE H 1 tEL Q V 2 29 tEHAX 11 tEHI CC L 7 tEHQ Z E 27 6 t ELQ X G t AV QV 4 t G L QV 9 tGH Q Z 3 8 tG L Q X DQ (D ATA OUT) 10 tELI CC H DAT A VAL ID AC T IVE ICC ST AND BY Document Control #ML0061 Rev 1.1 Jan, 2008 6 Simtek Confidential Preliminary SRAM WRITE CYCLES #1, #2, and #3 SYMBOLS NO. #1 15 16 17 18 19 20 21 22 23 24 25 tAVAV tWLWH tELWH tBLWH tDVWH tWHDX tAVWH tAVWL tWHAX t WLQZ e, g tWHQX #2 tAVAV tWLEH tELEH tBLEH tDVEH tEHDX tAVEH tAVEL tEHAX #3 tAVAV tWLBH tELBH tBLBH tDVBH tBHDX tAVBH tAVBL tBHAX tDW tDH tAW tAS tWR tWZ tOW Alt. tWC tWP tCW Write Cycle Time Write Pulse Width Chip Enable to End of Write Byte Enable to End of Write Data Set-up to End of Write Data Hold after End of Write Address Set-up to End of Write Address Set-up to Start of Write Address Hold after End of Write Write Enable to Output Disable Output Active after End of Write 3 PARAMETER MIN 15 10 15 15 5 0 10 0 0 7 3 MAX MIN 25 20 20 20 10 0 20 0 0 STK14EC16-15 STK14EC16 STK14EC16-25 MAX STK14EC16-45 UNITS MIN 45 30 30 30 15 0 30 0 0 10 3 15 MAX ns ns ns ns ns ns ns ns ns ns ns Note g: If W is low when E goes low, the outputs remain in the high-impedance state. Note h: E or W must be VIH during address transitions. SRAM WRITE CYCLE #1: W Controlledg,h tAVAV (15) Address Address Valid tELWH (17) tWHAX (23) E tBLWH (18) LB, UB W tAVWL (22) Data Input tWLQZ (24) Data Output Previous Data tAVWH (21) tWLWH (16) tDVWH (19) tWHDX (20) Input Data Valid tWHQX (25) High Impedance SRAM WRITE CYCLE #2: E Controlledg,h tAVAV (15) Address tAVWL (22) E tBLEH (18) LB , UB tWLEH (16) W Data Input tDVEH (19) tEHDX (20) Address Valid tELEH (17) tEHAX (23) Input Data Valid High Impedance Data Output Document Control #ML0061 Rev 1.1 Jan, 2008 7 Simtek Confidential STK14EC16 SRAM WRITE CYCLE #3: LB, UB Controlledg,h t AVAV (15) Preliminary Address E t AVBL Address Valid t ELBH (17) (22) t BLBH (18) t BHAX (23) LB , UB t AVBH (21) t WLBH (16) W t DVBH (19) Data Input Data Output t BHDX (20) Input Data Valid High Impedance AutoStoreTM/POWER-UP RECALL SYMBOLS NO. Standard 26 27 28 29 tHRECALL tSTORE VSWITCH VCCRISE tHLHZ Alternate Power-up RECALL Duration STORE Cycle Duration Low Voltage Trigger Level VCC Rise Time 150 PARAMETER MIN MAX 20 12.5 2.65 ms ms V s i j STK14EC16 UNITS NOTES Note i: Note j: tHRECALL starts from the time VCC rises above VSWITCH If an SRAM WRITE has not taken place since the last nonvolatile cycle, no STORE will take place AutoStoreTM/POWER-UP RECALL VCC VSWITCH (28) tVCCRISE (29) AutoStore POWER-UP RECALL Read & Write Inhibited ** tSTORE (27) ** tSTORE (27) tHRECALL (26) tHRECALL (26) POWER-UP BROWN OUT POWER-UP Read & Write POWER DOWN Read & Write AutoStore RECALL RECALL AutoStore ** AutoStore occures only if at least one SRAM Write has happened Note: Read and Write cycles will be ignored during STORE, RECALL and while VCC is below VSWITCH Document Control #ML0061 Rev 1.1 Jan, 2008 8 Simtek Confidential Preliminary SOFTWARE-CONTROLLED STORE/RECALL CYCLEk.l Symbols NO. 30 31 32 33 34 E Contk tAVAV tAVEL tELEH tEHAX tRECALL G Contk tAVAV tAVGL tGLGH tGHAX tRECALL PARAMETER Alternate tRC tAS tCW STORE/RECALL Initiation Cycle Time Address Set-up Time Clock Pulse Width Address Hold Time RECALL Duration MIN 15 0 12 1 150 MAX MIN 25 0 20 1 150 MAX STK14EC16-15 STK14EC16-25 STK14EC16 STK14EC16-45 UNITS NOTES MIN 45 0 30 1 150 MAX ns ns ns ns s l Note k: The software sequence is clocked on the falling edge of E controlled READs or G controlled READs Note l: The six consecutive addresses must be read in the order listed in the Software STORE/RECALL Mode Selection Table. W must be high during all six consecutive E or G controlled cycles. SOFTWARE STORE/RECALL CYCLE: E CONTROLLEDl 30 t AVAV ADDRESS 31 t AVEL ADDRESS #1 30 t AVAV ADDRESS #6 E 32 t ELEH G 33 tEHAX Deby 27 t STORE DATA VALID /t 34 RECALL HIGH IMPEDENCE DQ (DATA) DATA VALID SOFTWARE STORE/RECALL CYCLE: G CONTROLLEDl 30 t AVAV ADDRESS ADDRESS #1 30 t AVAV ADDRESS #6 E Pachuco Boys 31 t AVGL 32 t GLGH G 27 t STORE 33 tGHAX DQ (DATA) DATA VALID DATA VALID / 34 t RECALL HIGH IMPEDENCE Document Control #ML0061 Rev 1.1 Jan, 2008 9 Simtek Confidential STK14EC16 HARDWARE STORE CYCLE SYMBOLS PARAMETER Standard 35 36 tDELAY tHLHX Alternate tHLQZ Hardware STORE to SRAM Disabled Hardware STORE Pulse Width tDELAY Preliminary STK14EC16 UNITS MIN 1 15 MAX 70 s ns m NOTES Note m: On a hardware STORE initiation, SRAM operation continues to be enabled for time to allow read/write cycles to complete HARDWARE STORE CYCLE 36 t HLHX HSB (IN) 27 t STORE HSB (OUT) 35 t DELAY DQ (DATA OUT) SRAM Enabled SRAM Enabled Soft Sequence Commands NO. SYMBOLS Standard 37 tSS Soft Sequence Processing Time PARAMETER STK14EC16 MIN MAX 70 s n,o UNITS NOTES Note n: This is the amount of time that it takes to take action on a soft sequence command. Vcc power must remain high to effectively register command. Note o: Commands like Store and Recall lock out I/O until operation is complete which further increases this time. See specific command. 33 tss Soft Sequence Command ADDRESS ADDRESS #1 ADDRESS #6 33 tss Soft Sequence Command ADDRESS #1 ADDRESS #6 Vcc Document Control #ML0061 Rev 1.1 Jan, 2008 10 Simtek Confidential Preliminary MODE SELECTION STK14EC16 G, UB, LB A17-A0 X X X 0x04E38 0x0B1C7 0x083E0 0x07C1F 0x0703F 0x08B45 0x04E38 0x0B1C7 0x083E0 0x07C1F 0x0703F 0x04B46 0x04E38 0x0B1C7 0x083E0 0x07C1F 0x0703F 0x08FC0 0x04E38 0x0B1C7 0x083E0 0x07C1F 0x0703F 0x04C63 E W Mode I/O Power Notes H L L X H L X L X Not Selected Read SRAM Write SRAM Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM AutoStore Disable Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM AutoStore Enable Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM Nonvolatile Store Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM Nonvolatile Recall Output High Z Output Data Input Data Output Data Output Data Output Data Output Data Output Data Output Data Output Data Output Data Output Data Output Data Output Data Output Data Output Data Output Data Output Data Output Data Output Data Output High Z Output Data Output Data Output Data Output Data Output Data Output High Z Standby Active Active L H L Active p,q,r L H L Active p,q,r L H L Active p,q,r ICC2 L H L Active p,q,r Note p: The six consecutive addresses must be in the order listed. W must be high during all six consecutive cycles to enable a nonvolatile cycle. Note q: While there are 18 addresses on the STK14EC16, only the lower 16 are used to control software modes Note r: I/O state depends on the state of G, UB, and LB. The I/O table shown assumes G, UB, and LB low. Document Control #ML0061 Rev 1.1 Jan, 2008 11 Simtek Confidential STK14EC16 nvSRAM OPERATION nvSRAM The STK14EC16 nvSRAM is made up of two functional components paired in the same physical cell. These are the SRAM memory cell and a nonvolatile QuantumTrap cell. The SRAM memory cell operates like a standard fast static RAM. Data in the SRAM can be transferred to the nonvolatile cell (the STORE operation), or from the nonvolatile cell to SRAM (the RECALL operation). This unique architecture allows all cells to be stored and recalled in parallel. During the STORE and RECALL operations SRAM READ and WRITE operations are inhibited. The STK14EC16 supports unlimited read and writes like a typical SRAM. In addition, it provides unlimited RECALL operations from the nonvolatile cells and up to 200K STORE operations. Preliminary It is recommended that G be kept high during the entire WRITE cycle to avoid data bus contention on common I/O lines. If G is left low, internal circuitry will turn off the output buffers tWLQZ after W goes low. AutoStore OPERATION The STK14EC16 stores data to nvSRAM using one of three storage operations. These three operations are Hardware Store (activated by HSB), Software Store (activated by an address sequence), and AutoStore (on power down). AutoStore operation is a unique feature of Simtek Quantum Trap technology that is enabled by default on the STK14EC16. During normal operation, the device will draw current from VCC to charge a capacitor connected to the VCAP pin. This stored charge will be used by the chip to perform a single STORE operation. If the voltage on the VCC pin drops below VSWITCH, the part will automatically disconnect the VCAP pin from VCC. A STORE operation will be initiated with power provided by the VCAP capacitor. Figure 3 shows the proper connection of the storage capacitor (VCAP) for automatic store operation. Refer to the DC CHARACTERISTICS table for the size of the capacitor. The voltage on the VCAP pin is driven to 3.6V by a regulator on the chip. A pull up should be placed on W to hold it inactive during power up.This pull-up is only effective if the W signal SRAM READ The STK14EC16 performs a READ cycle whenever E and G are low while W and HSB are high. The address specified on pins A0-17 determine which of the 262,144 data words will be accessed. Byte enables (UB, LB) determine which bytes are enabled to the output. When the READ is initiated by an address transition, the outputs will be valid after a delay of tAVQV (READ cycle #1). If the READ is initiated by E and G, the outputs will be valid at tELQV or at tGLQV, whichever is later (READ cycle #2). The data outputs will repeatedly respond to address changes within the tAVQV access time without the need for transitions on any control input pins, and will remain valid until another address change or until E or G is brought high, or W and HSB is brought low. SRAM WRITE A WRITE cycle is performed whenever E and W are low and HSB is high. The address inputs must be stable prior to entering the WRITE cycle and must remain stable until either E or W goes high at the end of the cycle. The data on the common I/O pins DQ0-15 will be written into memory if it is valid tDVWH before the end of a W controlled WRITE or tDVEH before the end of an E controlled WRITE. The Byte Enable inputs (UB, LB) determine which bytes are written. 0.1F vCC vCC 10K Ohm vCAP vCAP W Figure 3. AutoStore Mode Document Control #ML0061 Rev 1.1 Jan, 2008 12 Simtek Confidential Preliminary is tri-state during power up. Many MPU's will tri-state their controls on power up. This should be verified when using the pullup. When the nvSRAM comes out on power-on-recall, the MPU must be active or the W held inactive until the MPU comes out of reset. To reduce unneeded nonvolatile stores, AutoStore and Hardware Store operations will be ignored unless at least one WRITE operation has taken place since the most recent STORE or RECALL cycle. Software initiated STORE cycles are performed regardless of whether a WRITE operation has taken place. The HSB signal can be monitored by the system to detect an AutoStore cycle is in progress. STK14EC16 SOFTWARE STORE Data can be transferred from the SRAM to the nonvolatile memory by a software address sequence. The STK14EC16 software STORE cycle is initiated by executing sequential E controlled or G controlled READ cycles from six specific address locations in exact order. During the STORE cycle, previous data is erased and then the new data is programmed into the nonvolatile elements. Once a STORE cycle is initiated, further memory inputs and outputs are disabled until the cycle is completed. To initiate the software STORE cycle, the following READ sequence must be performed: 1 Read Address 2 Read Address 3 Read Address 4 Read Address 5 Read Address 6 Read Address 0x4E38 0x83E0 0x703F Valid READ Valid READ Valid READ HARDWARE STORE (HSB) OPERATION The STK14EC16 provides the HSB pin for controlling and acknowledging the STORE operations. The HSB pin can be used to request a hardware STORE cycle. When the HSB pin is driven low, the STK14EC8 will conditionally initiate a STORE operation after tDELAY. An actual STORE cycle will only begin if a WRITE to the SRAM took place since the last STORE or RECALL cycle. The HSB pin has a very resistive pullup and is internally driven low to indicate a busy condition while the STORE (initiated by any means) is in progress. This pin should be externally pulled up if it is used to drive other inputs. SRAM READ and WRITE operations that are in progress when HSB is driven low by any means are given time to complete before the STORE operation is initiated. After HSB goes low, the STK14EC16 will continue to allow SRAM operations for tDELAY. During tDELAY, multiple SRAM READ operations may take place. If a WRITE is in progress when HSB is pulled low, it will be allowed a time, tDELAY, to complete. However, any SRAM WRITE cycles requested after HSB goes low will be inhibited until HSB returns high. If HSB is not used, it should be left unconnected. 0xB1C7 Valid READ 0x7C1F Valid READ 0x8FC0 Initiate STORE Cycle Once the sixth address in the sequence has been entered, the STORE cycle will commence and the chip will be disabled. It is important that READ cycles and not WRITE cycles be used in the sequence and that G, UB, and LB are active. After the tSTORE cycle time has been fulfilled, the SRAM will again be activated for READ and WRITE operation. SOFTWARE RECALL Data can be transferred from the nonvolatile memory to the SRAM by a software address sequence. A software RECALL cycle is initiated with a sequence of READ operations in a manner similar to the software STORE initiation. To initiate the RECALL cycle, the following sequence of E controlled or G controlled READ operations must be performed: 1 Read Address 2 Read Address 3 Read Address 4 Read Address 5 Read Address 6 Read Address 0x4E38 0x83E0 0x703F 0x4C63 Valid READ Valid READ Valid READ Initiate RECALL Cycle 0xB1C7 Valid READ 0x7C1F Valid READ HARDWARE RECALL (POWER-UP) During power up or after any low-power condition (VCC Document Control #ML0061 Rev 1.1 Jan, 2008 13 Simtek Confidential STK14EC16 After the tRECALL cycle time, the SRAM will once again be ready for READ or WRITE operations. The RECALL operation in no way alters the data in the nonvolatile storage elements.Care must be taken so the controlling falling edge is glitch and ring free so as not to double clock the read address. Preliminary * Power up boot firmware routines should rewrite the nvSRAM into the desired state (autostore enabled, etc.). While the nvSRAM is shipped in a preset state, best practice is to again rewrite the nvSRAM into the desired state as a safeguard against events that might flip the bit inadvertently (program bugs, incoming inspection routines, etc.). * The autostore enabled/disabled feature will reset to "autostore enabled" on every power down event captured by the nvSRAM. The application firmware should disable autostore on each reset sequence that this behavior is desired. * The Vcap value specified in this datasheet includes a minimum and a maximum value size. Best practice is to meet this requirement and not exceed the max Vcap value because the nvSRAM internal algorithm calculates Vcap charge time based on this max Vcap value. Customers that want to use a larger Vcap value to make sure there is extra store charge and store time should discuss their Vcap size selection with Simtek to understand any impact on the Vcap voltage level at the end of a tRECALL period. DATA PROTECTION The STK14EC16 protects data from corruption during low-voltage conditions by inhibiting all externally initiated STORE and WRITE operations. The lowvoltage condition is detected when VCC The STK14EC16 is a high-speed memory and so must have a high-frequency bypass capacitor of 0.1 F connected between both VCC pins and VSS ground plane with no plane break to chip VSS. Use leads and traces that are as short as possible. As with all high-speed CMOS ICs, careful routing of power, ground, and signals will reduce circuit noise. LOW AVERAGE ACTIVE POWER CMOS technology provides the STK14EC16 with the benefit of power supply current that scales with cycle time. Less current will be drawn as the memory cycle time becomes longer than 50 ns. Figure 4 shows the relationship between ICC and READ/ WRITE cycle time. Worst-case current consumption is shown for commercial temperature range, VCC=3.6V, and chip enable at maximum frequency. Only standby current is drawn when the chip is disabled. The overall average current drawn by the STK14EC16 depends on the following items: 1 2 3 4 5 6 The duty cycle of chip enable The overall cycle rate for operations The ratio of READs to WRITEs The operating temperature The VCC Level I/O Loading BEST PRACTICES nvSRAM products have been used effectively for over 15 years. While ease-of-use is one of the product's main system values, experience gained working with hundreds of applications has resulted in the following suggestions as best practices: * The non-volatile cells in this nvSRAM product are delivered from Simtek with 0x00 written in all cells. Incoming inspection routines at customer or contract manufacturer's sites will sometimes reprogram these values. Final NV patterns are typically complex 4-byte pattern of 46 E6 49 53 hex or more random bytes. End product's firmware should not assume an NV array is in a set programmed state. Routines that check memory content values to determine first time system configuration, cold or warm boot status, etc. should always program a unique NV pattern (i.e., repeating 4-byte pattern of 46 E6 49 53 hex) as part of the final system manufacturing test to ensure these system routines work consistently. Document Control #ML0061 Rev 1.1 Jan, 2008 14 Simtek Confidential Preliminary STK14EC16 PREVENTING AUTOSTORE The AutoStore function can be disabled by initiating an AutoStore Disable sequence. A sequence of READ operations is performed in a manner similar to the software STORE initiation. To initiate the AutoStore Disable sequence, the following sequence of E controlled or G controlled READ operations must be performed: 1 Read Address 2 Read Address 3 Read Address 4 Read Address 5 Read Address 6 Read Address 0x4E38 0x83E0 0x703F 0x8B45 Valid READ Valid READ Valid READ AutoStore Disable 0xB1C7 Valid READ 0x7C1F Valid READ Figure 4 - Current vs Cycle Time The AutoStore can be re-enabled by initiating an AutoStore Enable sequence. A sequence of READ operations is performed in a manner similar to the software RECALL initiation. To initiate the AutoStore Enable sequence, the following sequence of E controlled or G controlled READ operations must be performed: 1 Read Address 2 Read Address 3 Read Address 4 Read Address 5 Read Address 6 Read Address 0x4E38 0x83E0 0x703F 0x4B46 Valid READ Valid READ Valid READ AutoStore Enable 0xB1C7 Valid READ 0x7C1F Valid READ If the AutoStore function is disabled or re-enabled, a manual STORE operation (Hardware or Software) needs to be issued to save the AutoStore state through subsequent power down cycles. The part comes from the factory with AutoStore enabled, but best design practice is to set the enable or disable state during each power-up sequence and not depend on this factory default condition. Simtek recommends users configure the part completely for the specific application. Document Control #ML0061 Rev 1.1 Jan, 2008 15 Simtek Confidential STK14EC16 ORDERING INFORMATION STK14EC16-T F 45 I TR Packing Option Blank = Tube TR = Tape and Reel Preliminary Temperature Range Blank = Commercial (0 to +70 C) I = Industrial (-40 to +85 C) Access Time 15 = 15 ns 25 = 25 ns 45 = 45 ns Lead Finish F = Nickel/Palladium/Gold (Ni/Pd/Au) Package T = Plastic 44-pin 400 mil TSOPII (32 mil pitch) U = Plastic 54-pin 400 mil TSOPII (32 mil pitch) B = Plastic 48-pin FBGA (Fine Pitch Ball Grid Array) Document Control #ML0061 Rev 1.1 Jan, 2008 16 Simtek Confidential Preliminary Ordering Codes Part Number 2TK14EC16-TF15 STK14EC16-TF15TR STK14EC16-TF25 STK14EC16-TF25TR STK14EC16-TF45 STK14EC16-TF45TR STK14EC16-UF15 STK14EC16-UF15TR STK14EC16-UF25 STK14EC16-UF25TR STK14EC16-UF45 STK14EC16-UF45TR STK14EC16-BF15 STK14EC16-BF15TR STK14EC16-BF25 STK14EC16-BF25TR STK14EC16-BF45 STK14EC16-BF45TR STK14EC16-TF15I STK14EC16-TF15ITR STK14EC16-TF25I STK14EC16-TF25ITR STK14EC16-TF45I STK14EC16-TF45ITR STK14EC16-UF15I STK14EC16-UF15ITR STK14EC16-UF25I STK14EC16-UF25ITR STK14EC16-UF45I STK14EC16-UF45ITR STK14EC16-BF15I STK14EC16-BF15ITR STK14EC16-BF25I STK14EC16-BF25ITR STK14EC16-BF45I STK14EC16-BF45ITR Description 3V 4M-16b AutoStore nvSRAM 3V 4M-16b AutoStore nvSRAM 3V 4M-16b AutoStore nvSRAM 3V 4M-16b AutoStore nvSRAM 3V 4M-16b AutoStore nvSRAM STK14EC16 Access Times 15 ns access time 15 ns access time 25 ns access time 25 ns access time 45 ns access time 45 ns access time 15 ns access time 15 ns access time 25 ns access time 25 ns access time 45 ns access time 45 ns access time 15 ns access time 15 ns access time 25 ns access time 25 ns access time 45 ns access time 45 ns access time 15 ns access time 15 ns access time 25 ns access time 25 ns access time 45 ns access time 45 ns access time 15 ns access time 15 ns access time 25 ns access time 25 ns access time 45 ns access time 45 ns access time 15 ns access time 15 ns access time 25 ns access time 25 ns access time 45 ns access time 45 ns access time Temperature Commercial Commercial Commercial Commercial Commercial Commercial Commercial Commercial Commercial Commercial Commercial Commercial Commercial Commercial Commercial Commercial Commercial Commercial Industrial Industrial Industrial Industrial Industrial Industrial Industrial Industrial Industrial Industrial Industrial Industrial Industrial Industrial Industrial Industrial Industrial Industrial TSOP44-400 TSOP44-400 TSOP44-400 TSOP44-400 TSOP44-400 3V 4M-16b AutoStore nvSRAM TSOP44-400 3V 4M-16b AutoStore nvSRAM TSOP54-400 3V 4M-16b AutoStore nvSRAM TSOP54-400 3V 4M-16b AutoStore nvSRAM 3V 4M-16b AutoStore nvSRAM 3V 4M-16b AutoStore nvSRAM 3V 4M-16b AutoStore nvSRAM 3V 4M-16b AutoStore nvSRAM 3V 4M-16b AutoStore nvSRAM 3V 4M-16b AutoStore nvSRAM 3V 4M-16b AutoStore nvSRAM 3V 4M-16b AutoStore nvSRAM 3V 4M-16b AutoStore nvSRAM 3V 4M-16b AutoStore nvSRAM 3V 4M-16b AutoStore nvSRAM 3V 4M-16b AutoStore nvSRAM 3V 4M-16b AutoStore nvSRAM 3V 4M-16b AutoStore nvSRAM 3V 4M-16b AutoStore nvSRAM 3V 4M-16b AutoStore nvSRAM 3V 4M-16b AutoStore nvSRAM 3V 4M-16b AutoStore nvSRAM 3V 4M-16b AutoStore nvSRAM 3V 4M-16b AutoStore nvSRAM 3V 4M-16b AutoStore nvSRAM 3V 4M-16b AutoStore nvSRAM 3V 4M-16b AutoStore nvSRAM 3V 4M-16b AutoStore nvSRAM 3V 4M-16b AutoStore nvSRAM 3V 4M-16b AutoStore nvSRAM 3V 4M-16b AutoStore nvSRAM TSOP54-400 TSOP54-400 TSOP54-400 TSOP54-400 FBGA48 FBGA48 FBGA48 FBGA48 FBGA48 FBGA48 TSOP44-400 TSOP44-400 TSOP44-400 TSOP44-400 TSOP44-400 TSOP44-400 TSOP54-400 TSOP54-400 TSOP54-400 TSOP54-400 TSOP54-400 TSOP54-400 FBGA48 FBGA48 FBGA48 FBGA48 FBGA48 FBGA48 Document Control #ML0061 Rev 1.1 Jan, 2008 17 Simtek Confidential STK14EC16 PACKAGE DIAGRAMS 54-Pin TSOPII Top View 27 Pin 1 Index 1 Preliminary 0.404 0.396 ( 10.262 10.058 ) ( 11.938 11.735 0.470 0.462 ) 28 0.886 0.878 54 ( 22.517 22.313 ) 0.404 10.262 0.396 10.058 ( ) 0 5 0.0235 0.0160 () 0.597 0.406 0.016 0.012 0.0315 (0.800) BSC ( 0.400 ) 0.300 Base Plane Seating Plane 0.004 (0.10) 0.047 0.039 ( 1.194 0.991 ) 0.729 0.721 ( 18.517 18.313 ) 0.150 0.050 ( 0.0059 0.0020 ) DIM = INCHES DIM = mm MIN MAX MIN MAX () 18 Simtek Confidential Document Control #ML0061 Rev 1.1 Jan, 2008 Preliminary 44-Pin TSOPII Pin 1 Index 1 STK14EC16 Top View 22 0.404 0.396 ( 10.262 10.058 ) ( 11.938 11.735 0.470 0.455 ) 23 44 0.404 0.396 () 10.262 10.058 0 5 0.0235 0.0160 () 0.597 0.406 0.0315 (0.800) BSC 0.016 0.012 ( 0.400 0.300 ) Base Plane Seating Plane 0.004 (0.10) 0.047 0.039 ( 1.194 0.991 ) 0.729 0.721 ( 18.517 18.313 ) 0.150 0.050 ( 0.0059 0.0020 ) DIM = INCHES DIM = mm MIN MAX MIN MAX () 19 Simtek Confidential Document Control #ML0061 Rev 1.1 Jan, 2008 STK14EC16 48-Ball FBGA Preliminary TOP VIEW BOTTOM VIEW O0.05 M C O0.25 M CA B A1 CORNER A1 CORNER 00.30 0.05(48X) 1 2 3 4 5 6 6 5 4 3 2 1 A B 0.75 + + A B C C 10.00 0.10 10.00 0.10 5.25 D E F G H D E 2.625 F G + + + H A B 6.00 0.10 A 1.875 0.75 3.75 B 0.15(4x) 6.00 0.10 0.53 0.05 0.21 0.05 0.25C 0.36 SEATING PLANE C 120 MAX Document Control #ML0061 Rev 1.1 Jan, 2008 20 Simtek Confidential 0.15C // Preliminary Document Revision History Rev 1.0 Date April 2007 Change Moved to Preliminary from Advance Information - - - - - - - - STK14EC16 made clear that nominal supply is 3.3V, not 3.0V (range 2.7V to 3.6V) modified language on pin description of HSB and NC. changed ISB from 1mA to 2mA. changed Icc3 from 8mA to 26mA clarified description language of Figure 3 clarified description language of Software Recall clarified description language of Preventing Autostore corrected typo on Industrial temp range: -45 to -40 1.1 January 2008 Made the following changes to the document - - - page 1: revised block diagram page 3: added new 48 FBGA information, bock diagram, and package diagram; added pin descriptions for pins E, LB, UB, and W. page 4: added thermal characteristics. In the DC Characteristics table, revised values for Icc2, Icc4, ISB, VIH, and VCAP;and changed Industrial Max Value of VCAP to 180 and revised VCAP notes. Added "(except HSB)" to notes for Output Logic "1" Voltage. page 6: in SRAM Read Cycles #1 & #2 table, revised description for tELQX and tEHQZ and changed Symbol #2 to tELEH for Read Cycle Time; updated SRAM Read Cycle #2 timing diagramand changed title to add G controlled. page 7: in SRAM Write Cycles, added symbol #3. page 8: added new SRAM Write Cycle #3. In AutoStore/Power-Up Recall table, changed max value for #27 (tSTORE) to 12.5. Revised AutoStore/Power-Up Recall section. page 9: in Software-Controlled Store/Recall Cycle table, revised values for tRECALL; revised the notes below the Software-Controlled Store/Recall Cycle diagram. page 11: in Mode Selection table, changed column to A17-A0. In the values in this column, added a zero after each instance of "0x"; changed AutoStore Enable value to 0x04B46. page 12: in Auto-Store Operation, deleted line about VCAP pin being driven to 5V by a charge pump internal to the chip. Also, Added Stefan's revised text (italics show revision): "Refer to the DC CHARACTERISTICS table for the size of the capacitor." page 13: under Hardware Store (HSB) Operation, revised first paragraph to read "The HSB pin has a very resistive pullup..." page 14: added best practices section. page 16: in Ordering Information, Lead Finish, replaced "Sn (Matte Tin) RoHS Compliant" with "Nickel/Palladium/Gold (Ni/Pd/Au)." Also, added "B = Plastic 48-pin FBGA (Fine Pitch Ball Grid Array)" to Finish. page 17: in Ordering Codes, added ordering information for 48 FBGA and added access times column. - - - - - - - - - - Document Control #ML0061 Rev 1.1 Jan, 2008 21 Simtek Confidential |
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